Over-sampling A/D, D/A converter

ABSTRACT

The hardware of an over-sampling A/D and D/A converter is provided, which hardware is capable of being operated with either kind of software: one corresponding to a first method in which the over-sampling ratio is fixed and the other corresponding to a second method in which the over-sampling ratio is variable. The value N 3  written on the pseudo-frequency-dividing-ratio-register  11  and the value N 4  written on the pseudo-over-sampling-ratio-register  21  are converted through a user interface into the frequency dividing ratio N 1  by the conversion circuit  12  and the converted result is written in the frequency-dividing-ratio-register  10.

TECHNICAL FIELD

The present invention relates to an over-sampling A/D (analog/digital)conversion apparatus and an over-sampling D/A (digital/analog)conversion apparatus, and in particular it relates to the settingfunction of a sampling frequency and an over-sampling rate.

BACKGROUND ART

There have been used an over-sampling A/D conversion technique and anover-sampling D/A conversion technique in which sampling is performed ofa certain signal with a higher sampling frequency than a predeterminedsampling frequency (Hereinafter the higher sampling frequency will bereferred to as an over-sampling frequency for the purpose ofdiscriminating it from the predetermined sampling frequency) to obtainthe predetermined sampling frequency in thinning the sampled data byfiltering in a digital manner.

According to the above technique, the quantization noise caused by aconversion error of an A/D or a D/A converter can be driven out to ahigher frequency range, so that it is made possible to convert a signalat a higher degree of accuracy than that of the A/D or D/A converter tobe used. In other words, the conversion accuracy requested to the A/D,or D/A converter for obtaining a predetermined conversion accuracy islightened.

Further, according to the above-mentioned technique, the sampling isperformed at a higher frequency than the predetermined samplingfrequency, so that a Nyquist frequency, that is, an aliasing frequencyat which aliasing is generated in a case of sampling becomes also high.Therefore, the characteristics requested to a prefilter for cutting-offfrequencies higher than the Nyquist frequency at an A/D conversion isalso lightened.

As mentioned in the above, in using A/D, D/A conversion technique byover-sampling, conversion accuracy can be upgraded and also the requiredcharacteristics for analog filters such as prefilters can be largelylightened.

In order to utilize the above mentioned A/D and D/A converters byconventional technique in various ways, sampling by various frequenciesmust be possible. In particular, in the case of a modem for performingdata communications through telephone lines, where the communicationspeed has to be variable corresponding to the states of a communicationline or to the kind of a protocol being supported by a person tocommunicate with, sampling by various frequencies must be possible. Forthat purpose, in many cases, operational parameters such as the samplingfrequencies are arranged to be set at variable frequencies. There havebeen two setting methods as a related art in classifying roughly: afirst method as shown in FIG. 11 in which the over-sampling frequency isvariable and the over-sampling ratio is fixed (bibliographies: “UCB1100Data Sheet”, Phillips, “TLC320AD50C Data Manual”, Texas Instrument,etc.), and a second method as shown in FIG. 13 in which bothover-sampling frequency and over-sampling ratio are variable(bibliographies: “STLC7550 Data sheet”, SGS-Thomson, etc.).

DISCLOSURE OF INVENTION

In the first method, the ratio of the over-sampling frequency to thesampling frequency is constant. Therefore, utilizing the characteristicsof a digital filter whose frequency characteristic is scaled by anoperating frequency, if a decimator is operated at an over-samplingfrequency, the frequency characteristic of the decimator whichattenuates the frequencies by higher than ½ of the sampling frequencycan be realized with a digital filter having a set of filteringcoefficients.

On the other hand, according to the second method, since theover-sampling ratio is variable, it is possible to select anover-sampling frequency having the best characteristics concerning anarbitrary sampling frequency and to bring out an optimum characteristic.However, in this method, the ratio of the over-sampling frequency to thesampling frequency is not constant, so that it is not possible toutilize the frequency characteristic of a digital filter which is scaledby an operating frequency, and the coefficients of digital filters haveto be designed for every sampling ratio, the filters which compose adecimator.

In these methods, the numbers of operating parameters to be set aredifferent from each other, so that the configurations of registers forsetting the operating parameters are naturally different as shown inFIGS. 12, 14 and 16. Therefore, it is not possible to make a system ofhardware operate in controlling correctly using the software developedfor another system of hardware. Therefore, it has been impossible to usea system of hardware in place of another system of hardware.

In consideration of the above circumstances, the object of the presentinvention is to offer the hardware to be used for an over-sampling A/Dor D/A converter which can be operated with the software developed foreither system of hardware. When the object of the present invention isachieved, it is made possible to realize a system of hardware which isable to replace the hardware developed for either method, which willlead to the cost down of the hardware by mass production.

In order to solve the problem in the conventional technique, followingmeans are taken in the present invention.

(1) The case where hardware has a configuration in which anover-sampling ratio is constant:

(a) In the case where hardware is operated with software based on thefirst method in which the over-sampling ratio is constant, a frequencydividing ratio is changed to a frequency dividing ratio and anover-sampling ratio, and the original oscillation frequency is dividedbased on the changed frequency dividing ratio and the over-samplingratio, and a decimator is set at the changed over-sampling ratio.

(b) In the case where hardware is operated with software based on thesecond method in which the over-sampling ratio is variable, the originaloscillation frequency is divided based on the frequency dividing ratioand the over-sampling ratio written or a register by the software, andthe decimator is set at the written over-sampling ratio.

(2) The case where the hardware has a configuration in whichover-sampling ratio is variable:

(a) In the case where hardware is operated with the software based onthe first method in which the over-sampling ratio is constant, afrequency dividing ratio is changed to a frequency dividing ratio and anover-sampling ratio, and the original oscillation frequency is dividedbased on the changed frequency dividing ratio and the over-samplingratio, and a decimeter is set at the changed over-sampling ratio.

(b) In the case where hardware is operated with the software based onthe second method in which the over-sampling ratio is variable, theoriginal oscillation frequency is divided based on the frequencydividing ratio and the over-sampling ratio written on a register by thesoftware, and the decimeter is set at the written over-sampling ratio.

In short, by converting the parameters in a register, it is madepossible to make the hardware in which the over-sampling ratio is fixedbe operated with either of the software corresponding to the firstmethod in which the over-sampling ratio is fixed or corresponding to thesecond method in which the over-sampling ratio is variable.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 shows a block diagram showing the configuration capable of beingoperated with the software in which the over-sampling ratio is variable.

FIG. 2 shows a block diagram showing the configuration capable of beingoperated with both kinds of software in which the over-sampling ratio isvariable or fixed.

FIG. 3 shows a block diagram showing the configuration to which a modechangeover function is added.

FIG. 4 shows the configuration of the register shown in FIG. 3.

FIG. 5 shows a block diagram showing the configuration in which a modechangeover register is provided.

FIG. 6 shows the configuration of the register shown in FIG. 5.

FIG. 7 shows a block diagram showing the configuration of the hardwareto be operated with the software corresponding to a frequency dividerhaving a two stage configuration.

FIG. 8 shows the configuration of the register shown in FIG. 7.

FIG. 9 shows a block diagram showing the hardware configuration in whichthe over-sampling ratio is variable.

FIG. 10 shows a block diagram showing a D/A conversion apparatus.

FIG. 11 shows a block diagram showing a conventional technique (fixedover-sampling ratio).

FIG. 12 shows the configuration of the register shown in FIG. 11.

FIG. 13 shows a block diagram showing a conventional technique (variableover-sampling ratio).

FIG. 14 shows the configuration of the register shown in FIG. 13.

FIG. 15 shows a block diagram showing a conventional technique(frequency divider of a two stage configuration).

FIG. 16 shows the configuration of the register shown in FIG. 15.

BEST MODE FOR CARRYING OUT THE INVENTION

In the following, the explanation about the embodiments according to thepresent invention will be given.

FIG. 1 shows a basic embodiment according to the present invention. Theembodiment is an example in which the hardware of a fixed over-samplingratio is operated with the software corresponding to the second methodof a variable over-sampling ratio.

A value N3 written on a pseudo-frequency-dividing-ratio-register 11through a user interface and a value N4 written on apseudo-over-sampling-ratio-register 21 are converted to a frequencydividing ratio N1 in the conversion circuit 12 and it is written on afrequency-dividing-ratio-register 10.

Where, there is a relation as shown below among N1, N2, N3 and N4.

N1=N3*N4/N2

Therefore, in order to generate N1 in converting N3 and N4, there aretwo ways: one is to execute the operation shown in the above expression,and the other is to convert from N3, N4 to N1 using a conversion table.The conversion method using a conversion table is effective for reducingthe circuit scale, in particular when the number of setting combinationsof N3 and N4 is limited.

The original oscillation frequency fclk generated in an oscillator 30 isfrequency-divided to 1/N1 by a frequency divider 31, and it becomes anover-sampling frequency fs1. It is further frequency-divided to 1/N2 bya frequency divider 32 and becomes a sampling frequency fs2.

An A/D converter 33 samples an input analog signal with an over-samplingfrequency fs1, and converts the signal to a digital signal. In thedecimator 34, a thinning operation is performed on the sampled inputsignal using the sampling frequency fs1 to change the frequency of thesignal to 1/N2, and the sampled signal is converted to a samplingfrequency fs2. In the thinning operation, to change the sampled inputsignal frequency to 1/N2, in order to prevent the generation ofaliasing, the decimator 34 has characteristics to sufficiently attenuatethe frequency components higher than fs2/2. Such characteristics areoften realized by a combination of digital type comb filters andlow-pass filters. In many cases, the thinning to produce the frequency1/N2 is not performed at one time, but is performed over a plurality ofstages. In this case, the product of thinning rates for the respectivestages becomes N2.

In the embodiment shown in FIG. 1, in order to be able to set aplurality of sampling frequencies, the value of N1 must be large.Therefore, the original oscillation frequency fclk, an output of theoscillator 30, that is, N1×N2×fs2 becomes a high value. Therefore, afrequency multiplier 35 as shown in FIG. 2 is added to multiply thefrequency to N5 times, which makes it possible to control the originaloscillation frequency fclk, an output of the oscillator 30, to be as lowas 1/N5. Owing to the above, the cost of the oscillator 30 can becontrolled low. A PLL (Phase Locked Loop) is widely used for thefrequency multiplier 35.

Among the N1, N2, N3, N4 and N5, following relation exists as shown byan expression shown below.

N1=N3*N4*N5/N2

FIG. 3 shows an embodiment in which the hardware in which sampling ratiois fixed is operated with both kinds of software: one corresponding tothe first method in which an over-sampling ratio is fixed, and the othercorresponding to the second method in which an over-sampling ratio isvariable.

In the present embodiment, it is arranged in such a manner that thehardware can be operated with either kind of software in changing overthe circuit by a mode changeover signal. At first, in a case where thesoftware corresponds to the first method in which the over-samplingratio is fixed, the mode changeover signal selects 1 and the value inputthrough a user interface is written as it is on afrequency-dividing-ratio-register 10. In a case where the softwarecorresponds to the second method in which the over-sampling ratio isvariable, the mode changeover signal selects 0, and the value N3 writtenon a pseudo-frequency-dividing-ratio-register 11 and the value N4written on a pseudo-over-sampling-ratio-register 21 through the userinterface are converted to the frequency dividing ratio N1 in aconversion circuit 12, and it is written on thefrequency-dividing-ratio-resister 10. In this embodiment, the modechangeover signal is assumed to be input from an external circuit as anindependent signal, and in a case where the A/D converter isincorporated in a LSI, the LSI will be provided with a pin for inputtingthe mode changeover signal.

FIG. 4 shows the configuration of a register in the embodiment shown inFIG. 3. In the present embodiment, thepseudo-frequency-dividing-ratio-register 11 and thepseudo-over-sampling-ratio-register 21 or thefrequency-dividing-ratio-register 10 are allotted to a part of bits of aregister word.

When the mode changeover signal is 0, that is, in a mode 0, thepseudo-frequency-dividing-ratio-register 11 and thepseudo-over-sampling-ratio-register 21 are allotted to a part of bits ina register word as shown in FIG. 4(1). In this mode, it is possible toset the operation of hardware according to a register writing format ofthe software corresponding to the second method in which theover-sampling ratio is variable.

When the mode changeover signal is 1, that is, in a mode 1, only thefrequency-dividing-ratio-register 10 is allotted to a part of bits of aregister word as shown in FIG. 4(2). In this mode, it is possible to setthe operation of the hardware according to a register writing format ofthe software corresponding to the first method in which theover-sampling ratio is fixed.

FIG. 5 shows an embodiment in which the mode changeover signal shown inFIG. 3 is given as a set value of a mode changeover register 13 throughthe user interface.

In the present embodiment, in the same manner as in the embodiment shownin FIG. 3, the hardware is capable of being operated with either kind ofthe software in switching the circuit according to the set value of themode changeover register 13. In the case where the software correspondsto the first method in which over-sampling ratio is fixed the set valueof the mode changeover register 13 is made 1 and the value input throughthe user interface is as it is written on thefrequency-dividing-ratio-register 10. In the case where the softwarecorresponds to the second method in which the over-sampling ratio isvariable, the set value of the mode changeover register 13 is made 0,and the value N3 written on the pseudo-frequency-dividing-ratio-register11 and the value N4 written on the pseudo-over-sampling-ratio-register21 are converted to the frequency dividing ratio N1 by the conversioncircuit 12, and it is written on the frequency-dividing-ratio-register10.

FIG. 6 shows the configuration of the register in the embodiment shownin FIG. 4. The mode changeover register 13 is allotted to the LSB (LeastSignificant Bit); however naturally, it can be allotted to any bit. Itmight be better to decide the allotment of the mode changeover register13 in consideration of the compatibility and conformity with theconventional method. In most cases, in both methods, the first and thesecond methods, some bits in a part of a register word are reserved forthe future development, and some of the reserved bits will be used forthe changeover register 13.

When the set value of the changeover register 13 is 0, that is, in themode 0, the pseudo-frequency-dividing-ratio-register 11 and thepseudo-over-sampling-ratio-register 21 shown in FIG. 6(1) are allottedto the bits in a part of a register word. In this mode, it is possibleto set the operation of hardware according to the register writingformat of the software corresponding to the second method in which theover-sampling ration is variable.

When the set value of the changeover register 13 is 1, that is, in themode 1, only the frequency-dividing-ratio-register 10 is allotted to thebits in a part of a register word as shown in FIG. 6(2). In this mode,it is possible to set the operation of hardware according to theregister writing format of the software corresponding to the firstmethod in which the over-sampling ratio is fixed.

FIG. 7 shows the second method in which over-sampling ratio is variable,wherein two stages of frequency dividers, 31 a and 31 b, as shown inFIG. 15 are provided and the hardware can be operated with the softwarecorresponding to a method in which respective frequency dividing ratios,N1 a and N1 b of the above frequency dividers, 31 a and 31 b, are set infrequency-dividing-ratio-registers, 10 a and 10 b. In this method, asshown in FIG. 15, the frequency-dividing-ratio-registers, 10 a and 10 b,and the over-sampling-ratio-register 20 are allotted to the bits in apart of a register word.

In the present embodiment, in the similar manner to the embodimentsshown in FIG. 3 and FIG. 5, the hardware can be operated with eitherkind of software in switching the set value of the changeover register13. In the case where software corresponds to the first method in whichthe over-sampling ratio is fixed, the set value of the mode changeoverregister will be made 1 and the value input through the user interfaceis as it is written onto the frequency-dividing-ratio-register 10. Inthe case where software corresponds to the second method in which theover-sampling ratio is variable, the set value of the mode changeoverregister 13 will be made 0 and the values, N3 a and N3 b, written ontothe pseudo-frequency-dividing-ratio-register and the value N4 writtenonto the pseudo-over-sampling-ratio-register 21 input through the userinterface are converted to the frequency dividing ratio N1 by theconversion circuit 12, and it is written onto thefrequency-dividing-ratio-register 10.

FIG. 8 shows the configuration of a register in the embodiment shown inFIG. 7. The mode changeover register 13 is allotted to the LSB (LeastSignificant Bit); however, naturally, it can be allotted to any otherbits. It might be better to decide the allotment of the mode changeoverregister 13 in consideration of the compatibility and the conformitywith the conventional method. In most cases, in both first and secondmethods, a part of bits are reserved for the future development, and apart of the reserved bits will be used for the mode changeover register13.

When the set value of the mode changeover register 13 is 0, that is, inthe mode 0, as shown in FIG. 8(1), thepseudo-frequency-dividing-ratio-registers 11 a and 11 b, and thepseudo-over-sampling-ratio-register 21 are allotted to the bits in apart of a register word. In this mode, it is made possible to set theoperation of the hardware according to the register writing format ofthe software corresponding to the second method in which theover-sampling ratio is variable.

When the set value of the mode changeover register 13 is 1, that is, inthe mode 1, as shown in FIG. 8(2), only thefrequency-dividing-ratio-register 10 is allotted in the bits in a partof a register word. In this mode, it is possible to set the operation ofthe hardware according to the register writing format of the softwarecorresponding to the first method in which the over-sampling ratio isfixed.

In the above, an embodiment is described in which the hardware having afixed over-sampling ratio can be operated with both kinds of software:one corresponding to the first method in which the over-sampling ratiois fixed and the other corresponding to the second method in which theover-sampling ratio is variable.

In contrast with this, it is also possible to operate the hardware inwhich over-sampling ratio is variable with both kinds of software: onecorresponding to the first method in which the over-sampling ratio isfixed and the other corresponding to the second method in which theover-sampling ratio is variable.

FIG. 9 shows an embodiment for the hardware in which the over-samplingratio is variable with the software corresponding to the first method inwhich over-sampling ratio is fixed. The value input through the userinterface and written in the pseudo-frequency-dividing-ratio-register 11us converted to the frequency dividing ratio N1 and the over-samplingratio N2 by the conversion circuit 12 and the results are written in thefrequency-dividing-ratio-register 10 and theover-sampling-ratio-register 20, respectively. The A/D conversionapparatus composed of the oscillator 30, frequency dividers 31 and 32,the A/D converter 33 and the decimator 34 is operated following thevalues of the frequency-dividing-ratio-register 10 and theover-sampling-ratio-register 20. As mentioned above, according to thepresent embodiment, it is possible to operate hardware in which theover-sampling ratio is variable with the software corresponding to thefirst method in which the over-sampling ratio is fixed. If the modechangeover register 13 is added as in the case of the embodiment shownin FIG. 3, it is possible to operate the hardware with both kinds ofsoftware by mode setting: one corresponding the first method in whichthe over-sampling ratio is fixed and the other corresponding to thesecond method in which the over-sampling ratio is variable.

In the above, the description about an A/D conversion apparatus isgiven; however the above-mentioned embodiment can be applied to anover-sampling D/A conversion, an inverse conversion to the above. FIG.10 shows the block diagram of the embodiment.

The value N3 written onto the pseudo-frequency-dividing-ratio-register11 and the value N4 written onto the pseudo-over-sampling-ratio-register21 are converted to the frequency dividing ratio N1 by the conversioncircuit 12 and written onto the frequency-dividing-ratio-register 10.

The original oscillation frequency fclk generated by the oscillator 30is frequency-divided by the frequency divider 31 to 1/N1 and becomes theover-sampling frequency fs1. Further, it is frequency-divided by thefrequency divider 21 to 1/N2 and becomes the sampling frequency fs2.

The interpolator 36 interpolates a signal of the sampling frequency fs2time-wise and converts it to a signal of the over-sampling frequencyfs1. In the case of interpolation, since an unnecessary frequencycomponent called an image is generated, in many cases, the interpolator36 is realized by the combination of comb filters and low-pass filtersin a digital form.

In many cases, interpolation to multiply a frequency N2 times is notperformed in a stage but over a plurality of stages. In such a case, theproduct of multiplication rates of respective stages becomes N2. Thesignal interpolated in the interpolator 36 in the last step, isconverted to an analog signal by the D/A converter 35. In the followingstage to the D/A converter 35, a post-filter (not shown in the drawing)is provided for eliminating the quantization noise generated in the caseof D/A conversion.

When the mode changeover register 13 is added as described in theembodiment shown in FIG. 3, the hardware can be operated with eithersoftware by mode setting: one corresponding to the first method in whichthe over-sampling ratio is fixed and the other corresponding to thesecond method in which the over-sampling ratio is variable.

As mentioned above, according to the present invention, the hardware forthe over-sampling A/D converter or D/A converter having a single unitconstitution can be operated with either kind of software: onecorresponding to the first method in which the over-sampling ratio isfixed and the other corresponding to the second method in which theover-sampling ratio is variable.

What is claimed is:
 1. A conversion apparatus comprising: anover-sampling-ratio-register and a frequency-dividing-ratio-registercapable of being set by a signal from an external circuit, wherein a newfrequency dividing ratio is generated based on the set values in saidfrequency-dividing-ratio-register and said over-sampling-ratio-register,and an original oscillation frequency is divided based on said generatedfrequency dividing ratio to form a sampling frequency.
 2. Adigital/analog conversion apparatus comprising: anover-sampling-ratio-register and a frequency-dividing-ratio-registercapable of being set by a signal from an external circuit, wherein a newfrequency dividing ratio is generated based on the set values in saidover-sampling-ratio-register and said frequency-dividing-ratio-register,and an original oscillation frequency is divided based on the generatedfrequency dividing ratio to form a sampling frequency.
 3. A conversionapparatus comprising: a pseudo-frequency-dividing-ratio-register; apseudo-over-sampling-ratio-register; afrequency-dividing-ratio-register; and a conversion circuit forconverting the values set in saidpseudo-frequency-dividing-ratio-register and saidpseudo-over-sampling-ratio-register to generate a set value of saidfrequency-dividing-ratio-register; wherein an original oscillationfrequency is divided based on the set value of saidfrequency-dividing-ratio register to form a sampling frequency.
 4. Aconversion apparatus according to claim 3, wherein in a case where amode changeover signal input from an external circuit is in a firststate, the value converted in said conversion circuit is made the setvalue of said frequency-dividing-ratio-register, and in a case where amode changeover signal input from an external circuit is in a secondstate, the value input from the external circuit is made the set valueof said frequency-dividing-ratio-register.
 5. A conversion apparatusaccording to claim 3, wherein said apparatus further comprises a modechangeover register, and the value input from an external circuit ismade the set value of said mode changeover register, in a case where theset value of said mode changeover register is in a first state, thevalue converted in said conversion circuit is made the set value of saidfrequency-dividing-ratio-register, and in a case where the set value ofsaid mode changeover register is in a second state, the value input froman external circuit is made the set value of saidfrequency-dividing-ratio-register.
 6. A conversion apparatus accordingto claim 5, wherein in a case where the set value of said modechangeover register is in a first state, said mode changeover registerand said pseudo-frequency-dividing-ratio or saidpseudo-over-sampling-ratio-register exist in the same register word, andin a case where the set value of said mode changeover register is in asecond state, said mode changeover register and saidfrequency-dividing-ratio-register exist in the same register word.
 7. Anover-sampling digital/analog conversion apparatus comprising: apseudo-frequency-dividing-ratio-register; apseudo-over-sampling-ratio-register; and afrequency-dividing-ratio-register; wherein the values set in saidpseudo-frequency-dividing-ratio-register and saidpseudo-over-sampling-ratio-register are converted to generate a setvalue of said frequency-dividing-ratio-register, and an originaloscillation frequency is divided based on the set value of saidfrequency-dividing-ratio-resister to form a sampling frequency.
 8. Anover-sampling digital/analog conversion apparatus according to claim 7,wherein in a case where a mode changeover signal input from an externalcircuit is in a first state, the value converted in said conversioncircuit is made the set value of said frequency-dividing-ratio-register,and in a case where a mode changeover signal input from the externalcircuit is in a second state, the value input from the external circuitis made the set value of said frequency-dividing-ratio-register.
 9. Anover-sampling digital/analog conversion apparatus according to claim 7,wherein said apparatus further comprises a mode changeover register andthe value input from the external circuit is made the set value of saidmode changeover register, in a case where the set value of said modechangeover register is in a first state, the value converted in saidconversion circuit is made the set value of saidfrequency-dividing-ratio-register, and in a case where the set value ofsaid mode changeover register is in a second state, the value input fromthe external circuit is made the set value of saidfrequency-dividing-ratio-register.
 10. An over-sampling digital/analogconversion apparatus according to claim 9, wherein in a case where theset value of said mode changeover register is in a first state, saidmode changeover register and saidpseudo-frequency-dividing-ratio-register or saidpseudo-over-sampling-ratio-register exist in the same register word, andin a case where the set value of said mode changeover register is in asecond state, said mode changeover register and saidfrequency-dividing-ratio-register exist in the same register word.
 11. Aconversion apparatus comprising: apseudo-frequency-dividing-ratio-register; anover-sampling-ratio-register; and a conversion circuit for convertingset values of said frequency-dividing-ratio-register and saidpseudo-frequency-dividing-ratio-register to generate set values of saidfrequency-dividing-ratio-register and said over-sampling-ratio-register;wherein an original oscillation frequency is divided to form a samplingfrequency, and a decimator is operated based on the set value of saidover-sampling-ratio-register.
 12. A conversion apparatus according toclaim 11, wherein in a case where a mode changeover signal input from anexternal circuit is in a first state, the value converted in saidconversion circuit is made the set value of saidfrequency-dividing-ratio-register and said over-sampling-ratio-register,and in a case where a mode changeover signal input from the externalcircuit is in a second state, the value input from the external circuitis made the set values of said frequency-dividing-ratio-register andsaid over-sampling-ratio-register.
 13. A conversion apparatus accordingto claim 11, wherein said apparatus further comprises a mode changeoverregister and a value input from an external circuit is made the setvalue of said mode changeover register, in a case where the set value ofsaid mode changeover register is in a first state, the value convertedin said conversion circuit is made a set value of saidfrequency-dividing-ratio-register and said over-sampling-ratio-register,and in a case where the set value of said mode changeover register is ina second state, the value input from the external circuit is made a setvalue of said frequency-dividing-ratio-register and saidover-sampling-ratio-register.
 14. A conversion apparatus according toclaim 13, wherein in a case where the set value of said mode changeoverregister is in a first state, said mode changeover register and saidpseudo-frequency-ratio-register exist in the same register word, and ina case where the set value of said changeover register is in a secondstate, said mode changeover register and saidfrequency-dividing-ratio-register or said over-sampling-ration-registerexist in the same register word.
 15. An over-sampling digital/analogconversion apparatus comprising: apseudo-frequency-dividing-ratio-register; anover-sampling-ratio-register; and a conversion circuit for convertingset values of the frequency-dividing-ratio-register and thepseudo-frequency-dividing-ratio-register to generate set values of saidfrequency-dividing-ratio-register and said over-sampling-ratio-register;wherein an original oscillation frequency is divided based on a setvalue of said frequency-dividing-ratio-register to form a samplingfrequency, and an interpolator is operated based on the set values ofsaid over-sampling-ratio-register.
 16. An over-sampling digital/analogconversion apparatus according to claim 15, wherein in a case where amode changeover signal input from an external circuit is in a firststate, a value converted in said conversion circuit is made the setvalues of said frequency-dividing-ratio-register and saidover-sampling-ratio-register, and in a case where a mode changeoversignal input from a external circuit is in a second state, the valueinput from the external circuit is made the set value of saidfrequency-dividing-ratio-register and said over-sampling-ratio-register.17. An over-sampling digital/analog conversion apparatus according toclaim 15, wherein said apparatus further comprises a mode changeoverregister and the value input from an external circuit is made the setvalue of said mode changeover register, in a case where the set value ofsaid mode changeover register is in a first state, a value converted insaid conversion circuit is made the set values of saidfrequency-dividing-ratio-register and said over-sampling-ratio-register,and in a case where the set value of said mode changeover register is ina second state, a value input from the external circuit is made the setvalues of said frequency-dividing-ratio-register and saidover-sampling-ratio-register.
 18. An over-sampling digital/analogconversion apparatus according to claim 17, wherein in a case where theset value of said mode changeover register is in a first state, saidmode changeover register and saidpseudo-frequency-dividing-ratio-register exist in the same registerword, and in a case where the set value of said mode changeover registeris in a second state, said mode changeover register and saidfrequency-dividing-ratio-register or said over-sampling-ratio-registerexist in the same register word.
 19. A conversion apparatus according toclaim 1, wherein said conversion apparatus is an analog/digitalconversion apparatus.
 20. A conversion apparatus according to claim 1,wherein said conversion apparatus is a digital/analog conversionapparatus.
 21. A conversion apparatus according to claim 3, wherein saidconversion apparatus is an over-sampling analog/digital conversionapparatus.
 22. A conversion apparatus according to claim 11, whereinsaid conversion apparatus is an over-sampling analog/digital conversionapparatus.